QUATECH, INC. WSB-100 VER. 1 Card Type Waveform Synthesizer Chipset/Controller Intel I/O Options Analog/Clock/Digital/Strobe I/O ports Maximum DRAM N/A [Image] CONNECTIONS Purpose Location Purpose Location Analog output CN1 Module signal CN5 connector Strobe/clock/trigger CN2 Multi-board CN6 connector data connector Strobe/clock/trigger CN3 Multi-board CN7 connector control connector Module power connector CN4 I/O ADDRESS CONFIGURATION Address SW1 SW2 » 300h 1, 2, 3, 4, 5 & 6 3, 4, 5 & 6 on on 330h 1, 2, 3, 4, 5 & 6 3 & 4 on 2A60hh 1, 2, 4 & 6 on 2, 3 & 6 on Note: The address range for the WSB-100 is from 0 to FFFFh. The switches are a binary representation of the addresses. The switches have the following decimal values: SW1/1=8, SW1/2=4, SW1/3=2, SW1/4=1, SW1/5=8, SW1/6=4, SW2/1=2, SW2/2=1, SW2/3=8, SW2/4=4, SW2/5=2, SW2/6=1, The DMM-100 requires sixteen consecutive address locations. OPERATING MODE CONFIGURATION Mode J1 J2 Single board 1 & 11, 2 & 12, 3 & 13, 1 & 9, 2 & 10, 3 & 11, 4 system 4 & 14, 5 & 15, 6 & 16, & 12, 5 & 13, 7 & 17, 8 & 18, 9 & 19, 10 & 20 closed 6 & 14, 7 & 15, 8 & 16 closed OPERATING MODE CONFIGURATION Mode J1 J2 Single board system 1 & 11, 2 & 12, 3 & 1 & 9, 2 & 10, 3 & 11, with delayed trigger 13, 4 & 14, 5 & 15, 6 4 & 12, 5 & 13, 14 & & 16, 7 & 17, 8 & 18, 22, 7 & 15, 8 & 16 9 & 19, 10 & 20 closed closed Simultaneous output - 1 & 11, 2 & 12, 3 & 9 & 17, 2 & 10, 3 & master board 13, 4 & 14, 5 & 15, 6 11, 4 & 12, 5 & 13, 6 & 16, 9 & 19, 10 & 20 & 14, 15 & 23, 16 & 24 closed closed 7, 17, 27, 8, 18 & 28 open Simultaneous output - 1 & 11, 12 & 22, 13 & 9 & 17, 2 & 10, 3 & slave board 23,14 & 24, 11, 4 & 12, 5 & 13, 6 & 14, 15 & 23, 8 & 16 15 & 25, 16 & 26, 19 closed & 29, 20 & 30 closed 7, 17, 27, 8, 18 & 28 open Master/slave mode - 1 & 11, 2 & 12, 3 & 9 & 17, 10 & 18, 11 & master board 13, 4 & 14, 5 & 15, 6 19, 12 & 20, & 16, 7 & 17, 8 & 18, 9 & 19, 10 & 20 5 & 13, 6 & 14, 7 & closed 15, 8 & 16 closed Master/slave mode - 11 & 21, 12 & 22, 13 9 & 17, 10 & 18, 11 & slave board & 23, 14 & 24, 19, 12 & 20, 15 & 25, 16 & 26, 17 5 & 13, 6 & 14, 7 & & 27, 18 & 28, 15, 8 & 16 closed 19 & 29, 20 & 30 closed Slave interrupting 1 & 11, 2 & 12, 3 & 9 & 17, 2 & 10, 11 & mode - master board 13, 4 & 14, 5 & 15, 6 19, 4 & 12, & 16, 7 & 17, 8 & 18, 9 & 19, 10 & 20 5 & 13, 6 & 14, 7 & closed 15, 8 & 16 closed Slave interrupting 1 & 11, 12 & 22, 13 & 9 & 17, 2 & 10, 3 & mode - slave board 23, 14 & 24, 11, 4 & 12, 15 & 25, 16 & 26, 17 13 & 21, 6 & 14, 7 & & 27, 18 & 28, 15, 8 & 16 closed 19 & 29, 20 & 30 closed EXTERNAL CLOCK Source/Clock J3 J4 J5 CN2/clock 1 pins 1 & 4 N/A pins 5 & 6 closed closed CN3/clock 2 N/A pins 1 & 4 pins 2 & 3 closed closed TRIGGER SOURCE Source J3 J4 J5 CN2 pins 3 & 6 N/A pins 5 & 6 closed closed CN3 N/A pins 3 & 6 pins 2 & 3 closed closed TRIGGER CLOCK Source J3 J4 J5 CN2 pins 2 & 5 N/A pins 5 & 6 closed closed CN3 N/A pins 2 & 5 pins 2 & 3 closed closed CN2 I/O CONFIGURATION I/O J3 J5 Clock 1 input pins 1 & 4 closed pins 5 & 6 closed Trigger delay clock pins 2 & 5 closed pins 5 & 6 closed input CN2 I/O CONFIGURATION I/O J3 J5 External trigger input pins 3 & 6 closed pins 5 & 6 closed Data rate clock output N/A pins 4 & 5 closed CN3 I/O CONFIGURATION I/O J4 J5 Clock 2 input pins 1 & 4 closed pins 2 & 3 closed Trigger delay clock pins 2 & 5 closed pins 2 & 3 closed input External trigger input pins 3 & 6 closed pins 2 & 3 closed Data rate clock output N/A pins 1 & 2 closed DMA SELECT Setting J6 » DMA 5 pins 3 & 6 closed DMA 6 pins 2 & 5 closed DMA 7 pins 1 & 4 closed INTERRUPT SELECT IRQ J7 J8 IRQ3 N/A pins 1 & 7 closed IRQ4 N/A pins 2 & 8 closed IRQ5 N/A pins 3 & 9 closed IRQ6 N/A pins 4 & 10 closed IRQ7 N/A pins 5 & 11 closed IRQ9 N/A pins 6 & 12 closed IRQ10 pins 5 & 10 closed N/A IRQ11 pins 4 & 9 closed N/A IRQ12 pins 3 & 8 closed N/A IRQ14 pins 2 & 7 closed N/A IRQ15 pins 1 & 6 closed N/A